Intel's Analog and Mixed Signal IP Group (AMSG) is looking for an talented and energetic Analog Engineering Manager to lead and grow in the rapidly growing high performance power delivery/Voltage Regulator/Low Drop Out/Bandgap IP space for Intel's flagship client/server/chipset/Graphics SOC designs. This is a second level management position in which you will manage, grow and provide mentoring to a cross site analog design team consisting of First level managers, analog Design Engineers and Mask Designers. You and your group's responsibilities will include but not be limited to:

- Managing and growing a cross site analog team with strong track record and expertise

- Working with Intel technology and research teams to enable future generation IP requirements

- Working closely with other teams such as logic design, physical design, design automation, IP/collateral providers

- Planning, providing resources for and directing activities in engineering function to meet schedules, standards, and cost

- Cultivating and reinforcing appropriate group values, norms and behaviors

- Identifying and analyzing problems, plans, tasks, and solutions

- Providing guidance on employee development, performance, and productivity issues.

- Setting strategic direction and building a strong technical organization

- Cultivating an innovative and creative environment

- Supervising managers/engineers, planning assignments, monitoring tasks for successful completion, performance management and coaching 

Qualifications

Minimum Requirements:

Candidate should have MS or PhD in Electrical Engineering or Computer Engineering, with a minimum 10-12 years of experience in analog or mixed-signal circuit design. This experience must include at least 4-5 years in a managerial capacity. Past experience should include managing a design team of more than 10 engineers spanning execution control, team development, strategic direction and building a strong technical organization. Some experience coaching and/or supervising technical leads and first line managers preferred. Additional qualifications include:

• Experience hiring and growing a team
• Proven track record in the complete life cycle of deep sub-micron analog mixed signal IP product from definition, design, tapeout, debug, testing, yield analysis, to product qualification
• Strong analog design experience with high efficiency VR/LDO, high performance AD/DA, SerDes IO, PLL/DLL, etc
• Strong experiences with mixed signal design flow and modeling techniques, and knowledge about structural design and analog layout
• Highly motivated individuals and ability to deal with ambiguity
• Ability and experience to work with Intel external technology companies for combined IP development
• Ability to work in a tight schedule environment and deliver quality IP design
• Knowledge of analog IP, CPU and SOC architecture would be an added advantage 

The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Other Locations

US, Massachusetts, Hudson

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....