I currently work with Cyient
as V&V Engineer
I have years of experience working in the
Aviation/Aeronautics industry.
V&V Engineer Consultant|
BAE
From October 2019 to Current • 7 year(s)
FPGA Mission Keyboard and Control Panel project development with DO-254 Level C experience and RTVM requirements traceability.
V&V Engineer Consultant|
Cyient
From October 2018 to Current • 8 year(s)
Design verification of FPGA blocks including auditing Matlab function and VHDL models, requirements review and link tracing.
V&V Engineer Consultant|
L3
From October 2018 to October 2019 • 1 year(s)
FPGA Mission Keyboard and Control Panel project development with DO-254 Level C experience and RTVM requirements traceability.
V&V Engineer Consultant|
L3
From October 2016 to October 2018 • 2 year(s)
V model LCDP Life Cycle Development Process and RTVM Requirement Traceability Verification Matrix process development.
V&V Test Engineer Consultant|
GE
From May 2013 to October 2016 • 3 year(s)
Nuclear V model HLCD system level Verification and Validation support for HSIS, HRS, HDD and VHDL based testing.
DO-254 V & V Consultant|
Parker Aerospace
From February 2012 to February 2013 • 1 year(s)
Firmware Do-254 and SAE ARP4745 A V&V support engineer for Fly by Wire IIM system with FAA and EASA Certification support.
Remote OVM Verification Consultant|
Tek Place
From February 2011 to February 2012 • 1 year(s)
OVM, Verilog, C++ and Perl DFT design verification in Unix System and Product Environment with testbench development.
System Engineer Consultant|
Rockwell Collins
From February 2010 to January 2011 • 1 year(s)
ITAR System EMC, EMI and ENV Qualification support on Mil-Std products programs with test standards compliance.
V & V Engineer|
AAR Cargo Corp
From January 2009 to January 2010 • 1 year(s)
Validation and Verification on A400M aircraft Floor Based Handing System product with DOORS requirements support.
Systems Engineer|
Honeywell Inc.
From April 2008 to October 2008 • 0 year(s)
Verification on Honeywell aircraft Flight Control product with validation of derived design hardware and analysis.
Systems Engineer|
Enea Inc.
From February 2008 to April 2008 • 0 year(s)
GAP Audit of VM Methodology as defined in Life Cycle Product Development Plan covering FPGA requirements documentation.
Design Engineer|
Honeywell Inc.
From July 2007 to February 2008 • 1 year(s)
MKIIIG and MKII+ CMU LRU systems development and verification with systems requirements validation.
Verification Consultant|
Universal Avionics
From March 2007 to July 2007 • 0 year(s)
Firmware Do 254 Design Verification of two FPGA HDL Video CPLD's on contract basis.
System Verification Consultant|
Rockwell Collins
From December 2006 to March 2007 • 1 year(s)
Software Qualification and Regression testing for verification of RIU Unit module under Pro Line 21 integrated avionics.
Design Consultant|
Avidyne Corporation
From March 2006 to November 2006 • 0 year(s)
Tool Qualification Plan for ModelSim Simulator and VHDL code verification of ACTEL ProASIC+ APA600 MPIO FPGA.
Design Consultant|
Xytrans Corporation
From September 2005 to March 2006 • 1 year(s)
Design modification of Xilinx CPLD for SPI interface and VHDL code verification testing with hardware debug.
Design Verification|
Smiths Aerospace
From May 2005 to September 2005 • 0 year(s)
Verification methodology consulting for CPU's Airborne flight computer ASIC design based on IBM PowerPC 750GX microprocessor.
Design Verification|
Tandel Systems
From January 2005 to May 2005 • 0 year(s)
RVM verification methodology consulting for three ASIC Aerospace chip design with AMBA multi interface testbench generation.
Design Verification|
Intellon Corp
From May 2004 to January 2005 • 1 year(s)
Verification methodology consulting with Vera socket interface development within testbench to support Vera and RVM.
Design Application Engineer|
VidTech Inc
From February 2002 to May 2004 • 2 year(s)
Product and Customer Support for proprietary IO controller with team leadership and FPGA hardware design.
Consulting Software Application Engineer|
Verisity Design Inc
From June 2001 to February 2002 • 1 year(s)
Verification methodology consulting and technology product support with prototype RVM verification environments.
Verification Engineer|
Vixs System Inc
From March 2001 to June 2001 • 0 year(s)
Life Cycle Design Methodology and Verification Methodology for ASIC Design Department with verification design specification.
Verification Engineer|
IBM RTP
From November 2000 to March 2001 • 1 year(s)
Verification and test approaches for full system level critical dataflow for Transport Physical Communication layer.
Design Engineer|
Fairchild Semiconductor
From July 2000 to November 2000 • 0 year(s)
Design and simulate RTL for CMOS/BiCMOS high performance Interface products using Cadence simulation tools.
Verification Engineer|
Analog Devices
From January 2000 to July 2000 • 0 year(s)
Integration of 219x peripherals Agents blocks into top-level test environment with ABEL Simulation Environment verification.
